Non-Blocking Assignments (Toggle Flip-Flop Exampl)

Clock Skew explained very beutifully.

Visit:  ASIC Verification: Clock Skew

Ripple Carry Adder in Verilog

1 bit Full Adder behavioral Model

module fa_1b(input a, input b, input c_in, output reg sum, output reg c_out);

   always @ (a or b or c_in)

     {c_out, sum} = a + b + c_in;

endmodule

4 bit Ripple Carry Adder using 1 bit Full Adder

module rca_4bit(input [3:0] a, input [3:0] b, input c_in, output [4:0] sum);

   wire c1, c2, c3;

   fa_1b fa1(.a(a[0]), .b(b[0]), .c_in(c_in), .sum(sum[0]), .c_out(c1));

   fa_1b fa2(.a(a[1]), .b(b[1]), .c_in(c1), .sum(sum[1]), .c_out(c2));

   fa_1b fa3(.a(a[2]), .b(b[2]), .c_in(c2), .sum(sum[2]), .c_out(c3));

   fa_1b fa4(.a(a[3]), .b(b[3]), .c_in(c3), .sum(sum[3]), .c_out(sum[4]));

endmodule // rca_4bit

Testbench for 4 bit Ripple Carry Adder

module rca_tb();

   reg [3:0] a;

   reg [3:0] b;

   reg c_in;

   wire [4:0] sum;

   integer i, j, k, num_correct, num_wrong;

   reg [4:0] check;

   reg [8:0] rand;

   /* Unomment the version to test */

   rca_4bit ra4b (.a(a), .b(b), .c_in(c_in), .sum(sum)); /* Testing Ripple Carry Adder */

      

   initial begin

      num_correct = 0;

      num_wrong = 0;

      /* Doing exhaustive testing total number of cases are 2^4 * 2^4 * 2 = 512 */

      /* Only some random values will be printed */

      $display("\n\n===Testing 4 bit Ripple Carry Adder ===\n");

      $display("Printing Some random cases only\n");

      $display("c_in + a + b = sum (correct)\n");

      for(k=0; k<=1; k=k+1) begin c_in = k;

for(i=0; i<16; i=i+1) begin

   a = i;

   for(j=0; j<16; j=j+1) begin

      b = j;

      check[4:0] = a + b + c_in;

      #10

/* Display some random values */

rand[8:0] = $random;

        if(rand[8:5] == 4'b1001) $display("%b + %d + %d = %d (%d) ", c_in, a, b, sum, check);

      /* Counter for exhaustive testing */

      if(sum == check) num_correct = num_correct + 1;

      else num_wrong = num_wrong + 1;

   end

end

      end

      $display("Num Correct = %d\nNum Wrong = %d", num_correct, num_wrong);

      $display("\n==========================================================\n\n");

   end

endmodule

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